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Flipflop: The Store Room of Data

Sep 062015

A flipflop circuit is a binary cell capable of storing 1 bit information as it can store either 0 or 1 at any time, it can also be called ‘bistable multi-vibrator’. It has two outputs, one for normal value and the other for the complemented value of the bit that is stored in it.

There are varieties of flipflops used in electronic devices. They are described below:

1. RS Flipflop:

It is a basic type of flip-flop constructed using either NOR gates or NAND gates in cross-connected form. The two possible constructions of this type of flipflops are in the following figures. The cross-coupled form shown in the figure constitutes the feedback. This type of flipflop can also be called as direct coupled RS flipflop or SR latch as it doesn’t have any clock input. The R and S represent ‘reset’ and ‘set’ inputs respectively.

Characteristic Table for RS Flipflop

To analyze the operation of the above circuit, we must keep in mind that the output of a NOR gate is 0, if any input is 1 and the output is 1 only when all the inputs are 0. Initially, assume S = 1 and R = 0. Since gate 2 has an input 1, its output Q’ must be 0. Due to this, both inputs of gate 1 are at 0 and hence, Q is 1. When the set input is returned to 0 (S = 0 and R = 0), the output remains the same, as Q is 1, leaving one input of gate to equal to 1. Due to this, Q’ becomes 0 and hence, both the inputs of gate 1 are 0, due to which Q is 1.When 1 is applied to both the set and reset inputs, both Q and Q’ are equal to 0, which violates the fact that the outputs Q and Q’ are the complements of each other. For any flipflop, when Q = 1 and Q’ = 0, it is called to be in ‘set’ state. When Q = 0 and Q’ = 1, it is called ‘reset’ state or ‘clear’.

Characteristic Table for NAND gate based SR Latch

The operation is same as that of NOR gate and we should keep in mind that when one of the inputs is 0, the output is 1.

2. Clocked RS Flipflop:

Characteristic Table for Clocked RS Flipflop

Graphic Symbol

The basic flipflop is an asynchronous circuit. By adding gates to the input of basic circuit, the flipflop can be made to respond to the input levels during the occurrence of a clock pulse. The basic circuit diagram of clocked RS flipflop is shown in the figure given above. As in the figure, the outputs of the two AND gates remain zero as long as CP (Clock Pulse) remains zero, regardless of the S and R input values. When the clock pulse goes to 1, information from the S and R inputs reaches to the basic flipflop. The graphic symbol, as in the figure given above, contains three inputs, S, CP and R. The output of flipflops are marked with Q and Q’. The characteristic table or truth table gives the nature of normal output after the clock pulse is applied. Q is the binary state of flipflop at a given time, referred to as present state and Q(t+1) is the state of the flipflop after the occurrence of a clock pulse and is referred to as next state. The characteristic equation of the flipflop, derived from the k-map, specifies the value of next state as a function of present state and the inputs.

3. D Flipflop:

Graphic Symbol

The D flipflop is the modification of the clocked RS flipflop. As in the figure given above, D flipflop contains only two inputs, D and CP. The D input goes directly to the S input and its complement to the R input. As long as CP is 0, the 3 and 4 bits have a 1 in their outputs regardless of the value of D input. From the truth table of D flipflop, we can say that the output of D flipflop is same as that of the input D. The D in D flipflop represents its ability to transfer data without any change. It is basically as RS flipflop with an inverter in the R input.

4. JK Flipflop:

Graphic Symbol

A JK flipflop is the modified form of RS flipflop in the sense that the indeterminate state of RS flipflop is defined. The inputs J and K behave like inputs S and R to set and clear the flipflop. When the inputs J and K of the JK flipflop are the same simultaneously and are equal to 1, the flipflop switches to its complement of the current state, i.e. if Q = 1, it changes as Q(t + 1) = 0 and vice versa. The logic diagram of JK flipflop is shown in the figure given above. The Q output is ANDed with K and CP input and Q’ is ANDed with J and CP.
So, according to the characteristic table, the JK flipflop behaves like an RS flipflop except when both J and K are equal to 1. When both J and K are 1, the clock pulse is transmitted through one AND gate only, the one whose input is connected to the flipflop output which is presently equal to 1. Thus, if Q = 1, the output of the upper AND gate becomes 1 and the flipflop is reset. If Q’ = 1, the output of the lower AND gate becomes 1, when J = 1, the flipflop is set. In each case, the output state of the flipflop is complemented. This is called toggling of JK flipflop and is defined only when J = 1 and K = 1. The JK flipflop with inputs J = 1 and K = 1 is said to be in toggle mode.
Note that, in JK flipflop, when a CP signal is equal to 1 while J = K = 1, after the outputs have been complemented once, may cause the repeated and continuous transition of output. This problem is called race condition. To avoid this undesirable operation, the clock pulse must have a time duration which is smaller than propagation delay of the flipflop. The restriction on the pulse width is eliminated with the Master Slave Flipflop.

5. T Flipflop:

Graphic Symbol

The T flipflop is a single input JK flipflop. It is obtained from JK flipflop when J and K inputs are the same. The name ‘T’ comes from the ability of this device to toggle or change the current state when its input is one.

Triggering of Flipflop: The state of a flipflop is switched by the momentary change in input signal. The change in this signal upon which the operation of a flipflop is largely dependent is called a trigger and the process is called triggering. The clock pulse is basically a trigger signal which starts from 0, remains 0 for a certain time and changes to 1, remains 1 for a certain time and returns back to 0. The change of the clock pulse from one level to another is called transition. The flipflops are responsive to such transitions.
A clock pulse may either be positive or negative. The pulse goes through two signal transitions, i.e. from 0 to 1 and from 1 to 0. As in the following figure, the transition from 0 to 1 gives the positive edge and the transition from 1 to 0 gives the negative edge.

6. JK Master Slave Flipflop:

A master slave flipflop is constructed from two separate flipflops. One circuit serves as a master and the other as a slave and the overall circuit is referred to as a master slave flipflop. It consists of an inverter along with two flipflops. When CP is 0, the output of the inverter is 1. In this case, as the clock input of the slave is 1, the flipflop is enabled and the output Q is equal to Y and Q’ is equal to Y’. The master flipflop at this time is disabled as CP = 0. When CP = 1, the information is transmitted to the slave from master flipflop. As the second flipflop just copies the information given by the output of the first flipflop, this setup is called master slave flipflop.

Microprocessor Architecture

Information Technology No Responses »

Aug 252015

Microprocessor architecture can be defined as the set of basic rules that define the components of a microprocessor, their organization, along with the way of functioning of those components for operation. In this post, we are describing about two different microprocessor architectures. They are:

Von Neumann Architecture: This approach is also known as ‘stored program concept’ and was first adopted by John Von Neumann.
The main memory is used to store data and instructions. The ALU is capable of performing arithmetic and logical operations on binary data. The program control unit interprets the instructions in memory and causes them to be executed. The I/O unit gets operated from control unit.
The Von Neumann architecture is the fundamental basis for the architecture of today’s digital computers. Thus, it is important to have an idea of internal structure of the CPU and CU of Von Neumann machine.
The memory of Von Neumann machine consists of 1000 storage locations called words, of 40 bits each. Both the data and instructions are stored in it. The CU operates the computer by fetching instructions from the memory and executing them one at a time.
The storage location of CU and ALU are called registers. The various registers of this model are:

Memory Buffer Register (MBR): It consists of words to be stored in memory or is used to receive a word from the memory.
Memory Address Register (MAR): It contains the address in memory of the word to be written from or read into MBR.
Instruction Register (IR): It contains 8 bit opcode being executed.
IBR (Instruction Buffer Register): It is used to temporarily hold the instructions from word in memory.
Program Counter (PC): It contains the address of the next instruction to be fetched from the memory.
The accumulator (A) and the multiplier quotient (MQ) are employed to temporarily hold the operands and the result of ALU operations.

In Von Neumann architecture, the same memory is used for storing instructions and data. Similarly, a single bus, either data bus or address buss is used for reading data and instructions from or writing data and instruction to the memory.
Later, it was revealed that this feature of Von Neumann architecture limited the processing speed of the computer. So, to improve the processing speed of computer, Harvard architecture was introduced.

Harvard Architecture: The Harvard architecture consists of separate memory locations for the programs and data. Each memory space has its own address and data bus. As a result of this, both the instructions, and data can be fetched from the memory concurrently. Thus, a significant processing speed is observed over Von Neumann type architecture.
From the figure, we can see that there are two data and two address buses for the program and data memory space separately. The program memory data bus and data memory bus are multiplexed to form single data bus whereas program memory address bus and data memory address bus are multiplexed to form a single address bus. Hence, there are two blocks of RAM chip, one for program memory and the other for data memory space. The data memory address arithmetic unit generates the data memory address. The data memory address bus carries the memory address of the data whereas the program memory address bus carries the memory address of the instruction. There is central arithmetic logic unit which consists of ALU, multiplier, accumulator and scaling chief register. The program counter is used to address program memory. The contents are updated following each decode operation. The control unit controls the sequence of operations to be executed. The data and control bus are bidirectional whereas the address bus is unidirectional.

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